As CMOS density scaling continues the region between adjacent gates becomes smaller, the silicide contact area decreases and the access resistance to the device increases. These factors tend to decrease the potential performance of the devices. Additionally, the geometry of a deep Source/Drain (S/D) region of the device can negatively impact the electrostatic control of the channel by the gate.
Reference with regard to silicide contact area scaling can be made to, for example, “Challenges and Opportunities for High Performance 32 nm CMOS Technology” Sleight, J. W. Lauer, I. Dokumaci, O. Fried, D. M. Guo, D. Haran, B. Narasimha, S. Sheraw, C. Singh, D. Steigerwalt, M. Wang, X. Oldiges, P. Sadana, D. Sung, C. Y. Haensch, W. Khare, M., IEDM 2006, 11-13 Dec. 2006.